This invention relates to electronic circuits, and more specifically to a programmable logic array macro cell, specialized for certain classes of functions.
A programmable logic array (PLA) is a general purpose integrated circuit (IC) device which, at some stage of its manufacture, is customized or programmed to execute a userdefined logical function. As illustrated in FIG. 1, a conventional PLA cell 10 has input lines I1 through IM which are programmably connectable to the input lines of AND gates AG1 through AGR, which are arranged in a row or first "level" of logic called an AND plane, and which form logical product terms P1 through PR. AND plane product term output lines are programmably connectable to OR gates OG1 through OGN, which are arranged in a column or second level called an OR plane, and which provide logical sum-of-product signals on OR plane output lines S1 through SN. Some of OR plane output lines S1-SN may be coupled through clocked registers 25, 26 to return signals on feedback lines 27, 28 to AND plane input lines for array cell 10 to execute sequential logic operations.
To program array cell 10, the user defines gate input line connections, by way of a pattern for a mask used in a manufacturing step for a mask-programmed PLA, or by way of a "fuse plot" used by a programming machine to blow fuses in a field programmable logic array (FPLA) after manufacture.
PLAs are designed with various ratios of quantities of AND gates, OR gates, and programmable connections in input lines to the logic planes. One type of PLA, a programmable array logic device, for example a "PAL" (registered trademark of Monolithic Memories, Inc.) device, has array input lines programmably connectable to AND plane input lines, and AND plane product output lines fixedly connected to OR plane input lines, with D-type flip-flop output registers. Although D-type flip-flops are powerful, large state machine applications often require the more versatile JK flip-flop function, which starts with a present state value Qo, upon which two input signal values J and K operate to produce a next state value Qo', according to the following table 1:
TABLE 1 ______________________________________ J K Qo' ______________________________________ 0 0 Qo 0 1 0 1 0 1 1 1 .sup.--Qo ______________________________________
The JK function is commonly expressed in a first form as Qo'=JQo+KQo. It can be implemented by a circuit 30, Fig. 2, in which input signal K is inverted by inverter 34 into signal K and applied with previous state feedback signal Qo to AND gate 36, while signal Qo is inverted by inverter 33 and applied with input signal J to AND gate 35. AND gates 35 and 36 apply product signals JQo and KQo, respectively, to the input lines of OR gate 37, which forms next state signal Qo'=JQo+KQo.
The J and/or K signals received by circuit 30 input lines 31 and 32 can in turn be products J1 and K1 of sets of input signals J1a through J1z, and K1a through K1z, respectively, provided by AND gates 11 and 14, FIG. 2. Furthermore, signals J and K can be logical sums of product signals J1 through Jj, and K1 through Kk, which are formed from respective subsets of input signals (a,b, . . . , z) by AND gates 11 through 16 and OR gates 17 and 18 in a PLA device 10, FIG. 2, without output registers 25 and 26 of FIG. 1.
However, an IC 20, FIG. 2, adapted to execute the JK flip-flop function by using a logic array 10 with OR plane output lines connected to a dedicated JK flip-flop circuit 30 cannot provide output signals for functions other than the JK flip-flop function, which conflicts with the IC design goal of making maximum use of minimum circuit elements.
The capacity to be programmed initially to execute other functions is preserved by a PLA device in which a sum-of-products array performs the JK function and stores next state signal Qo' in a D-type flip-flop for output and/or feedback. However, an AND-OR-INVERT array implementation of the JK function Qo'=JQo+KQo requires passing signal K (or its factors Ka . . . Kz) through the array in a first cycle to obtain K, inverting signal K, and then passing inverse signal K through the array again in a second cycle, or through a second equivalent array, with signals J (or its factors Ja . . . Jz), Qo, and Qo, to obtain next state signal Qo'. Such a use of multiple cycles through an array, or of multiple arrays, is inefficient.
If K is a product of z factors Ka through Kz, K=(Ka*Kb* . . . *Kz), then, by DeMorgan's laws, K=(Ka+Kb+ . . . +Kz), and KQo=(Ka * Qo+Kb * Qo+ . . . +Kz * Qo). Based upon these identities, the JK flip-flop equation can be expressed in an equivalent second form, Qo'=(JQo+KaQo+KbQo+ . . . +KzQo). However. a circuit with fewer than z product terms cannot implement this second form of the JK function.
The JK flip-flop function can also be expressed in an equivalent third form: Qo'=Qo.sym.(JQo+KQo). This form avoids the inconvenience of obtaining K, by using an exclusive OR (XOR) gate.
Programmable array logic circuits as described in U.S. Pat. No. 4,124,989 to Birkner and Chua and assigned to Monolithic Memories, Inc. are partitioned into cells which include an AND-OR array with a D type flip-flop output register. In some embcdiments of that patent, cells include an XOR gate between OR gate output terminals and the D flip-flop input terminal. These prior art XOR cells, with multiple AND gates feeding each of two OR gates, are suited to implement bit-carrys for arithmetic operations. The third equivalent form of the JK function can be implemented by driving the XOR gate with the previous state output signal Qo applied, without any logical operation, through one of the OR gates and one associated AND gate, but this use of half the XOR cell is inefficient.
There remains a need, therefore, for a programmable array logic cell design optimized for uses such as a flip-flop, a counter, a state machine, or a parity detector.